Reductions in the size of semiconductor devices (e.g., a metal-oxide semiconductor device) have enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with the design of a transistor and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate of the transistor alters a resistance associated with the channel region, thereby affecting the performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow for an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.
To further enhance the performance of MOS devices, stress may be introduced in the channel regions of the MOS devices to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type metal-oxide-semiconductor (NMOS) device in a source-to-drain direction and to induce a compressive stress in the channel region of a p-type metal-oxide-semiconductor (PMOS) device in a source-to-drain direction.
A commonly used method for applying compressive stresses to the channel regions of PMOS devices is to grow SiGe stressors in the source and drain regions. Such a method typically includes forming a gate stack on a semiconductor substrate; forming gate spacers on sidewalls of the gate stack; forming recesses in the silicon substrate; and epitaxially growing SiGe stressors in the recesses. Since SiGe has a greater lattice constant than silicon, it applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor. Similarly, SiC stressors may be formed for NMOS devices. Since SiC has a smaller lattice constant than silicon, tensile stresses may be applied to the channel regions.
FIG. 1 illustrates a layout of a commonly used circuit, which includes PMOS devices 2 and 4 sharing common source 6. PMOS device 2 further includes gate poly 7 and drain region 8. PMOS device 4 further includes gate poly 9 and drain region 10. PMOS devices 2 and 4 are formed using conventional stressor formation processes, and thus common source 6 and drain regions 8 and 10 are SiGe stressors. To save the chip area, the connection to common source 6 is made through a soft connection, which includes SiGe line 12, N+ region 14 connected to SiGe line 12, and contacts 16. SiGe line 12 is formed simultaneously with the formation of common source 6 and drain regions 8 and 10. A silicide layer (not shown) is then formed on N+ region 14, SiGe line 12, common source 6 and drain regions 8 and 10.
Conventional stressor formation processes suffer drawbacks, however. FIG. 2 illustrates a cross-sectional view of the structure shown in FIG. 1, wherein the cross-sectional view is taken along line A-A′ in FIG. 1. Silicide layer 18 is formed across common source 6, SiGe line 12, and N+ regions 14. It has been found that in region 19, which is an interface region between SiGe line 12 and N+ region 14, the thickness of silicide layer 18 is significantly less than in other regions. This may be related to the fact that metals tend to form silicide with silicon better than germanium.
The reduction in thickness of silicide layer 18 in region 19 causes sheet resistance tailing. Ideally, if multiple samples with the structure shown in FIGS. 1 and 2 are measured, the sheet resistances of the samples, without tailing effect, should be within a relatively small range. If tailing effects occur, however, an increased percentage of the samples will have higher sheet resistances. It has been found that sheet resistances are directly related to the RC delays of the integrated circuits. The tailing effects will cause the increase in RC delay, and possibly function failure of the integrated circuits. A solution is thus needed.